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... Programmable Logic
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Highlights the newest CPLDs & FPGAs
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Contains innovative product news for the Embedded Electronic Designer community |
| The best Low Cost, Non-Volatile Logic |
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The LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK embedded block memories and Serial TAG memory and design security. The parts also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.
The MachXO family of crossover programmable logic devices (PLDs) combines CPLD and FPGA attributes together to optimally serve applications such as bus bridging, bus interface and control that traditionally were implemented in CPLDs or low capacity FPGAs. More of the Best: MachXO includes PLLs and embedded memory along with features you've come to expect in CPLDs
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New Release of Lattice FPGA Design Tools Extends Performance and Productivity |
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Lattice announced the immediate availability of its ispLEVER® 7.1 FPGA design tool suite. The new tool release delivers a number of new functional and performance-enhancing features, including the industry's first dedicated FPGA Simultaneous Switching Output (SSO) Analyzer. The SSO Analyzer enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. To enable designers to achieve higher levels of productivity, the ispLEVER 7.1 design tools also deliver up to 30% faster FPGA design compile times and now support multi-processor powered design compilation to achieve the fastest timing closure.
Datasheet: ispLever
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New CPLD family for small, low power and low cost portable products
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Standby current as low as 10µA with cool 1.8V core.
Lattice Semiconductor announced its new, ultra low power Complex Programmable Logic Devices (CPLD), the 1.8-volt ispMACH 4000ZE family. This second-generation in-system programmable CPLD family is ideal for low power, high volume portable applications, with typical standby current as low as 10µA. The cost optimized and feature rich ispMACH 4000ZE devices offer ultra-small, space saving chip scale Ball Grid Array (csBGA) package options, a new Power Guard feature that provides ultra-low system power, and new system integration capabilities, including an on-chip user oscillator and timer. The ispMACH 4000ZE family will be offered in four logic densities, from 32 to 256 macrocells. Samples of the first two devices, the 32-macrocell ispMACH 4032ZE and the 64-macrocell ispMACH 4064ZE, are available now.
Features
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Lattice ECP2M : The First Low-Cost FPGA with 3 Gbps SERDES
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Get more for less with Lattice's new LatticeECP2M family. No other low-cost
FPGA offers up to 16 SERDES channels with full-duplex serial data transfers at
rates up to 3.125 Gbps. Best of all, each SERDES channel operates on a cool
100mW at maximum speed.
The LatticeECP2M family offers even more, including up to 5,3 Mb of RAM, high-speed DSP blocks, 533 Mbps DDR2 memory interface and SPI4.2 support. Plus, 128-bit AES Encrypted Bitstream support and Transparent Field Reconfiguration allow you to keep your designs secure and easily upgradeable even after your product has shipped.
Features LatticeECP2/M Low-Cost FPGA
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Automotive versions of its flash-based, non-volatile FPGA family
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Lattice Semiconductor announced that automotive versions of its non-volatile 90nm Flash-based LatticeXP2™ FPGAs (Field Programmable Gate Array) have been characterized and qualified to meet the certification requirements of the AEC-Q100 standard as defined by the Automotive Electronics Council (AEC). Designated the LA (“Lattice Automotive”)-LatticeXP2 family, these production released devices join Lattice's four previously announced automotive LA versions of the MachXO™ Crossover Programmable Logic Devices, ispPAC®-POWR1014/A Programmable Power Manager Devices, ispMACH® 4000V and ispMACH 4000Z CPLDs. Production quantities of the new LA-LatticeXP2 devices will be available by the fourth quarter of 2008, and Lattice can provide standard PPAP (Production Part Approval Process) documentation now to automotive customers who require it.
Datasheet: Lattice automotive
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