Each kit contains an evaluation board with USB connector for both programming and power, ispLEVER Starter Design Software DVD, USB Cable, Documentation and Schematics and the latest Data CD. The on-board device is the LCMXO640C-3TN144C. All of this fits in a 145x130x35mm box.

MACHXO : Features & Selection Guide

The LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK embedded block memories and Serial TAG memory and design security. The parts also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.
LatticeXP2 Product Guide

Lattice's FreedomChip custom tests standard LatticeSC/M FPGAs to your specific design using proven ASIC scan-based test methodologies. This provides you with a high quality, cost reduced FPGA for high volume applications with prototypes available in mere weeks. FreedomChip provides you with the benefits of structured ASIC pricing at a fraction of the associated NRE, while avoiding the lengthy technical challenges and risks associated with a design conversion. Moreover, since it uses the same LatticeSC/M FPGA die and package, FreedomChip functionality, performance, signal integrity and power consumption characteristics are identical to the FPGA it replaces. Unlike other custom-tested FPGA approaches, the FreedomChip methodology incorporates high quality, scan based test methodologies utilizing unique in-built FPGA circuitry to provide the industry’s highest fault coverage for FPGAs. Verifiable fault coverage reports are available as part of the FreedomChip process.

Lattice recently rolled out the LatticeECP2M FPGA family, the industry's first low cost FPGAs offering high-speed embedded SERDES I/O plus a pre-engineered Physical Coding Sublayer (PCS) block. Based on the innovative LatticeECP2 low cost architecture, the new LatticeECP2M family has been developed on advanced 90nm CMOS technology utilizing 300mm wafers. Previously, high-speed embedded SERDES serial I/O with speeds over 3Gbps have been available only on relatively expensive high-end FPGAs. Integrating this capability into a low cost FPGA fabric makes this higher performance interface technology accessible to a much broader range of applications in rapidly emerging, cost-conscious markets such as high volume communications, consumer, automotive, video, and industrial equipment. Priced at approximately one-third the cost of competitive SERDES-based FPGAs, the LatticeECP2M FPGA family effectively bridges the price/performance gap between low-cost and high-end FPGAs.